Advanced Packaging
The real GPU bottleneck. Where a logic die, an interposer, and 8 stacks of HBM become one chip.
What this layer does
For most of semiconductor history, “the chip” was a single die in a plastic package. AI accelerators broke that model: an H200 or B200 package contains a large logic die, multiple stacks of HBM memory, and a silicon interposer that connects them with tens of thousands of micro-bumps. This is called 2.5D packaging — TSMC’s implementation is branded CoWoS (Chip-on-Wafer-on-Substrate). It is the single most-cited bottleneck on Nvidia’s ability to ship more GPUs.
Advanced packaging is its own industry: HBM stacking (with TSVs — through-silicon vias), interposer manufacturing, hybrid bonding, large-format ABF substrates, and the test/assembly equipment that makes it all work. Capex is exploding here precisely because it’s the constraint.
Sub-categories
The actual packaging step. TSMC dominates the AI accelerator packaging market; Intel and Samsung have alternatives.
The packaging houses that handle the non-leading-edge majority of the world’s chips, plus growing AI-adjacent work.
How HBM goes from individual DRAM die to a 12-high stack with thousands of TSVs. Driven by hybrid bonding adoption.
The high-layer-count organic substrate under the package. Capacity-constrained; lead times still 6–12 months.
The tools that perform bonding, dicing, molding, plating for advanced packages. The hybrid-bonder market is a real new growth pool.
Testing each die before and after packaging. AI accelerators have so many I/Os and so much memory that test time per chip has exploded.