Chip Design Software & IP
The duopolies you can’t design a modern chip without.
What this layer does
Before a chip can be fabricated, it has to be designed. That requires EDA software (electronic design automation: simulation, place & route, verification), pre-built IP blocks (CPU cores, memory controllers, PCIe/NVLink interfaces), and photomasks that physically encode the design on the wafer. Every accelerator at TSMC — Nvidia’s, Google’s TPU, AWS Trainium — runs on Synopsys or Cadence software and licenses Arm or Synopsys IP.
This is one of the most beautifully structured industries in tech: a Synopsys/Cadence duopoly in EDA, Arm in CPU IP, and three photomask producers. Customers can’t switch off easily, the products are mission-critical, and AI is increasing both seat count and licensing intensity.
Sub-categories
Simulators, formal verification, logic synthesis. Where the chip is born.
The tools that turn a logical design into actual transistor layouts on a real process node.
The instruction-set architectures and reference cores most modern SoCs are built around.
The IP blocks that handle PCIe, NVLink, USB, DDR/HBM controllers, SerDes — sold separately from CPU cores.
Physical glass “stencils” used in lithography. Each new node multiplies mask cost and complexity (3nm reticle sets >$20M).
Newer tools applying ML to chip design itself (Synopsys DSO.ai, Cadence Cerebrus). Higher-margin add-on layer atop core EDA.