The AI Infrastructure Stack
Overview  /  Tier V Silicon  /  Layer 11: Chip Design Software & IP
Sub-category 11.2

EDA Software (Back-End: Place & Route, Signoff)

The tools that turn a logical design into actual transistor layouts on a real process node.

Players

Players: Synopsys (IC Compiler, PrimeTime) SNPS, Cadence (Innovus, Tempus) CDNS, Siemens EDA (Calibre signoff) SIE.DE

Analysis coming soon — this page is scaffolding for deeper research into eda software (back-end: place & route, signoff).